The present invention relates generally to Complementary Metal Oxide Semiconductor (CMOS) devices and, more particularly, to CMOS integration on extremely thin silicon on insulator (ETSOI) with dual raised source and drain on both nFET and pFET.
CMOS technology is employed in almost every electronic circuit application. One type of CMOS technology employs Silicon-On-Insulator (SOI) substrates in place of conventional silicon. The benefit of SOI over conventional silicon is the reduced parasitic capacitance that leads to improved performance. The implementation of SOI technology has allowed for the continued scaling planar silicon technology.
Extremely Thin Silicon-On-Insulator (ETSOI) is a leading candidate for further continued scaling of planar silicon technology. However, the successful introduction of ETSOI in manufacturing requires integration of negative-type field effect transistors (nFET) and positive-type field effect transistors (pFET) with high performance and low leakage.
A key feature to improve performance and reduce series resistance in ETSOI is the use of raised source/drain (RSD) epitaxy. In RSD epitaxy, the source and drain regions are formed above the channel region to obtain low series resistance. Formation of RSD requires the use of spacers. Current approaches to RSD integration on ETSOI planar devices rely on differential spacer thickness on the nFET and the pFET.
A drawback of the nFET and the pFET having differential spacer thickness is that it increases the scale of the device. It is desirable to have to have the same spacer thickness on both the nFET and the pFET. There is a need for an improved CMOS device and method of manufacturing the same.